From: Tim Korb [jtk@cs.purdue.edu] Sent: Monday, April 20, 1998 4:05 PM To: Ed Coyle; Elias Houstis; Hank Dietz; Dan Marinescu; Phillip Rawles; Avi Kak; George Lee; Stephen Badylak; Chris Hoffmann; Richard Westerman; Alok Chaturvedi; Steve Hare; Bernard Engel; John Harbor; Elisa Sotelino; John Abraham; Sanford Fleeter; Thomas Downar; Gintaras Reklaitis; Matthew Krane; John Sullivan; Franz Frederick; Aditya Mathur; David Meyer; Larry Huggins; Chandrajit Bajaj; Robert Bernhard; Timothy Haley; Dennis Lyn Cc: t4e-investigators@cs.purdue.edu Subject: Intel T4E 98Q2 Order News Here is the new plan for our next round of Intel orders. There are three "big events" on the horizon that Intel wants us to take advantage of in the T4E program. The events are associated with the availability of three products: 1. Eight-way servers 2. Katmai processors (70 new MMX instructions to support 3D graphics) 3. Merced processors (64-bit architecture) I don't have release dates for these products, but the Katmai is a year away and I understand the Merced is still two years out. The eight-way servers are probably comparatively soon, but none of these products are available "now". Following the existing delivery schedule would not allow us to take advantage of these new technologies. So, Intel would like us to defer whatever orders we can until these products become available. They have asked that we re-evaluate our immediate needs and only order products that are necessary, for example, to fill existing committments. As a target, they would like us to defer about 70% of our CPU requests to later quarters. I have appended to the bottom of this message a chart that is a summary--for each project--of the numbers of systems we requested in the original proposal for the first year, how many of those systems we have received so far, and how many we would have expected to receive this quarter (finishing out year one). As you can see, in total we had planned to order about 258 CPUs this quarter. That number is to be reduced to about 75 CPUs. Since it is not reasonable to simply defer everyone's allocation by 70%, we're going to have to assess the needs of individual projects to find out which ones can defer their orders and which ones need some or all of their planned allocation immediately. I have suggested, and the T4E Executive Committee has agreed, to attempt a "self assessment", in which projects re-evaluate their needs in light of this request from Intel. Please think about how many systems your project needs now (for June delivery). Let me know your thoughts and I'll put together a combined analysis to see how we can meet this goal. Thanks, Tim PS. I am sending this message to all people on campus associated with the T4E projects. If you are not the "project contact" person (in the To: field of this message), please communicate your needs to the person who is. =========================================================================== The chart below shows the breakdown for Year 1 by project. The "p" columns (psing, pduals, and pquads) are the number of systems in the proposal. The "r" columns (rsing, rduals, and rquads) are the number of systems we asked for and received. The "pcpus" and "rcpus" are the number of CPUs proposed and received. The "diff" column shows what each proposal requested in CPUs minus how many they have actually received so far. In effect, it is the number of CPUs that each project is expecting to receive this quarter. code psing pduals pquads pcpus rsing rduals rquads rcpus diff A.01 99 0 5 119 0 21 1 46 73 A.02 39 0 5 59 39 0 0 39 20 A.03 7 0 5 27 4 2 2 16 11 B.01 7 0 9 43 12 2 1 20 23 B.02 0 0 6 24 8 0 2 16 8 B.03 6 8 0 22 9 3 0 15 7 B.04 0 3 3 18 2 2 0 6 12 B.05 0 3 0 6 0 1 0 2 4 B.06 5 14 4 49 5 11 3 39 10 B.07 0 0 1 4 0 0 1 4 0 C.01 15 0 2 23 5 1 1 11 12 C.02 0 5 1 14 0 1 1 6 8 C.03 10 1 0 12 4 1 0 6 6 C.04 0 9 1 22 0 0 0 0 22 C.05 0 2 1 8 1 0 1 5 3 C.06 0 3 0 6 0 1 0 2 4 C.07 8 2 1 16 6 1 0 8 8 C.08 3 1 0 5 2 0 0 2 3 C.09 0 0 1 4 0 0 1 4 0 C.10 0 4 4 24 0 3 1 10 14 C.11 0 2 0 4 0 2 0 4 0 C.12 8 3 0 14 7 2 0 11 3 C.13 4 1 1 10 4 1 1 10 0 D.01 5 1 0 7 6 1 0 8 -1 D.02 0 5 0 10 7 0 0 7 3 D.03 22 1 2 32 14 4 1 26 6 D.04 3 0 1 7 4 0 1 8 -1 Totals 241 68 53 589 139 60 18 331 258